1. Field of the Invention
The present invention relates to a configuration of a digital logic gate, and more particularly, to a high frequency logic gate.
2. Description of the Related Art
Along with continuous progress of electronic technique, it is the trend that digital system designs are to be faster, thinner and lighter. However, in order to have the logic gate operated normally, a higher input signal has to be fed into the conventional logic gate. Therefore, the conventional logic gate cannot be normally operated in the RF (Radio Frequency) band when the signals are very weak (e.g. 0.9-1.1V).
A logic gate using in the RF band had been proposed in the field. FIG. 1 schematically shows a configuration of a current-mode logic AND gate. Referring to FIG. 1, the configuration comprises the inputs A, −A, B, −B, the outputs C and −C, the transistors M1, M2, M3, and M4, the resistors R1 and R2, and a current source I. Wherein, the resistors R1 and R2 comprise a first terminal and a second terminal respectively, and the current source I comprises a first terminal and a second terminal. Input A is fed into a gate of the transistor M1. A source of the transistor M1 is electrically coupled to the first terminal of the current source I, a drain of the transistor M1 is electrically coupled to the output −C, which is also electrically coupled to the first terminal of the resistor R1 and a drain of the transistor M3. The input −A is fed into a gate of the transistor M2. A source of the transistor M2 is electrically coupled to the first terminal of the current source I, and a drain of the transistor M2 is electrically coupled to a source of the transistor M3 and a source of the transistor M4. Input B is fed into a gate of the transistor M3, and input −B is fed into a gate of the transistor M4. A drain of the transistor M4 is electrically coupled to the output C, which is electrically coupled to the first terminal of the resistor R2. The second terminals of the resistors R1 and R2 are electrically coupled to a voltage source Vdd, and a second terminal of the current source I is grounded. Wherein, inputs A and −A, B and −B are the reverse phase logic inputs, and outputs C and −C are the reverse phase logic outputs.
In the configuration, transistors M1 and M2 are the differential inputs of A and −A, and transistors M3 and M4 are the differential inputs of B and −B. Since the amplitude of the input voltage signal in RF band is very small, the transistors M1, M2, M3, and M4 are not completely turned off or turned on. Therefore, the transistors M1, M2, M3, and M4 are functionally equivalent to a differential amplifier, and the current source I is used as a bias current for obtaining the output signals C and −C. The configuration mentioned above is referred to as the conventional current mode logic. Although such configuration is operated well in the RF band in which the amplitude of the input voltage signal is very small, since the transistors M3 and M4 are electrically coupled to the transistor M2, such that the inputs B and −B must have one more DC level than the inputs A and −A. And the differential input pairs of A and −A, B and −B are not symmetric. In addition, a constant current is required for normal operation, thus there is DC-bias consumption even when the logic gate is idle. Currently, the portable electronic products are widely accepted, and the power consumption issue has become an essential criterion in the design of the IC (Integrated Circuit) chip, thus it is no doubt that the DC-bias consumption is a significant source of the power consumption. Therefore, it is important to design a high frequency logic gate capable of significantly reducing the power consumption.